Share and Export
Share and Export
Daniels, Brian and Farrell, Ronan (2006) Design Of High Frequency Digital Phase Locked Loops. In: UNSPECIFIED.
![[thumbnail of ISSC_bdaniels.pdf]](https://mu.eprints-hosting.org/style/images/fileicons/application_pdf.png "ISSC_bdaniels.pdf")
PDF
ISSC_bdaniels.pdf
Download (87kB)
Abstract
This paper considers the stability of high order Charge Pump
Phase Lock Loop (CP-PLL), proposing a novel means of
identifying stable regions for such systems. Traditional design
techniques are inefficient for high frequency, high order CPPLL
systems. This paper proposes an accurate and efficient
means of identifying stable regions for 2nd and 3rd order high
frequency (> 1GHz) CP-PLL. Using exact non-linear CP-PLL
responses it is shown that the proposed stability technique is a
significant improvement over existing linear methods.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | This paper is a postprint of a paper submitted to and accepted for publicatin in (journal/conference) and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library |
| Keywords: | Stability, Charge Pump, Phase Locked Loop, High Frequency. |
| Academic Unit: | Faculty of Science and Engineering > Electronic Engineering |
| Item ID: | 601 |
| Depositing User: | Ronan Farrell |
| Date Deposited: | 12 Jul 2007 |
| Publisher: | Institution of Engineering and Technology |
| Refereed: | Yes |
| Related URLs: | |
| URI: | https://mu.eprints-hosting.org/id/eprint/601 |
| Use Licence: | This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here |
Repository Staff Only (login required)
- Item control page
Downloads
Downloads per month over past year
