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Podsiadlik, Tomasz and Farrell, Ronan (2014) Time-Interleaved Sigma-Delta Modulators for FPGAs. IEEE Transactions on Circuits and Systems II: Express Briefs, 61 (10). pp. 808-812. ISSN 1549-7747
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Abstract
This brief describes and analyzes a technique of increasing a sampling rate in a sigma-delta (ΣΔ) modulator based on a discrete-time description, which is an extension of existing techniques of parallelization. The limitations in the signalto-noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of a low-pass ΣΔ modulator characterized by a short critical path is used in this brief to validate the technique. An implementation of a modulator shows the increase in the sampling rate from 100 to 400 MHz.
| Item Type: | Article |
|---|---|
| Keywords: | Sampling frequency; sigma-delta; time interleaved (TI); |
| Academic Unit: | Faculty of Science and Engineering > Electronic Engineering |
| Item ID: | 10288 |
| Identification Number: | 10.1109/TCSII.2014.2345293 |
| Depositing User: | Ronan Farrell |
| Date Deposited: | 05 Dec 2018 16:48 |
| Journal or Publication Title: | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Publisher: | Institute of Electrical and Electronics Engineers |
| Refereed: | Yes |
| Related URLs: | |
| URI: | https://mu.eprints-hosting.org/id/eprint/10288 |
| Use Licence: | This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here |
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