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McEvoy, Paul and Farrell, Ronan (2004) Built-In Test Engine For Memory Test. In: UNSPECIFIED.
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Abstract
In this paper we will present an on-chip
method for testing high performance memory
devices, that occupies minimal area and retains full
flexibility. This is achieved through microcode test
instructions and the associated on-chip state
machine. In addition, the proposed methodology
will enable at-speed testing of memory devices. The
relevancy of this work is placed in context with an
introduction to memory testing and the techniques
and algorithms generally used today.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | Copyright é 2005 IEEE.  Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of NUI Maynooth ePrints and eTheses Archive's products or services. Internal or personal use of this material is permitted. However, permission for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. |
| Keywords: | BIST, memory, at-speed, DFT |
| Academic Unit: | Faculty of Science and Engineering > Electronic Engineering |
| Item ID: | 589 |
| Depositing User: | Ronan Farrell |
| Date Deposited: | 04 Jul 2007 |
| Publisher: | IEEE: Institute of Electrical and Electronics Engineers |
| Refereed: | Yes |
| URI: | https://mu.eprints-hosting.org/id/eprint/589 |
| Use Licence: | This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here |
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