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Embedded Test Engine For Efficient At-Speed Scan Testing and Performance Binning of Microprocessors

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Lawlor, Eddie and Farrell, Ronan (2004) Embedded Test Engine For Efficient At-Speed Scan Testing and Performance Binning of Microprocessors. In: UNSPECIFIED.

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Abstract

In this paper a modified architecture for at-speed scan testing is presented. This new architecture addresses the trend in the semiconductor industry for increased at-speed structural testing. The proposed architecture offers reduced time for standard at-speed testing, and, in particular, substantial savings for the repeated atspeed testing required for microprocessor speed and performance binning. The architecture has been demonstrated on UMC 0.18μm and has achieved with little die overhead.

Item Type:	Conference or Workshop Item (Paper)
Additional Information:	Copyright © 2005 IEEE.   Reprinted from  (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of NUI Maynooth ePrints and eTheses Archive's products or services.  Internal or personal use of this material is permitted.  However, permission for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
Keywords:	at-speed scan testing, performance speed binning, design-for-test, embedded test.
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	588
Depositing User:	Ronan Farrell
Date Deposited:	04 Jul 2007
Publisher:	IEEE: Institute of Electrical and Electronics Engineers
Refereed:	Yes
URI:	https://mu.eprints-hosting.org/id/eprint/588
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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