This paper presents a realised prototype of fully integrated CMOS LC-PLL frequency syn- thesizer. The circuit delivers a wide range of clock signals between 12 MHz and 5800 MHz, with average long term jitter of only 4 ps. The primary application of the presented circuit includes high speed series data transmission links. Low power consumption of the complete synthesizer (including bias circuitry), in the range of 50mW from dual 1.2 V/3.3 V supply, is in line with energy efficient solutions for modern elec- tronic systems. The circuit is developed using a standard RF UMC 130 nm CMOS process reducing design time and necessity for customisation of its components. Full integration of RC loop filter is obtained us- ing dual path tuning scheme, involving two separate charge pumps, two filter paths and specially modified LC-VCO architecture. Total synthesizer area including PLL circuitry with set of programmable frequency divider, output RF drivers, two separate VCO circuits and all auxiliary bias circuitry occupies no more than 0.7 mm2 of active area.