In this research work we present a reconfigurable platform that implements all the digital processing and RF carrier generation for the class S Power Amplifier proposed by the Institute of Microelectronics and Wireless Systems. This amplifier is a combination of a lowpass or bandpass sigma-delta modulation stage in series with a frequency shifting stage and a switch mode amplifier followed by a band pass filter. The reconfigurable platform is parameterizable, scalable and it has been optimized for reconfigurable devices. It takes advantage from the Multi-Gigabit serial links embedded into the new FPGAs to synthesize binary RF signals, and from the parameterizable soft cores that the FPGA vendor provides. The implementation results for a stand-alone and for a tiny Wishbone compatible Systemon-Programmable-Chip versions are presented. The design is validated with data measured in the simulation and in the prototype.